1. Field of the Invention
The present invention relates to a combinatorial circuit for performing a combinatorial operation using a plurality of inputs signals in order to generate an output signal, and in particular to such a circuit for use in situations where a level shifting function also needs to be applied to the output signal.
2. Description of the Prior Art
A level shifter circuit is used when there is a need to pass signals from one voltage domain to a different voltage domain. In modern data processing systems, it is becoming more and more common for certain parts of the data processing system to operate in a different voltage domain to one or more other parts of the data processing system. For example, a trend within integrated circuits is the increasingly common use of embedded memory, such as SRAM memory. With the reduction in size of process geometries, the individual memory cells within the memory are becoming less stable. To reduce the power consumption of the integrated circuit, it is desirable to reduce the operating voltage of the components within the integrated circuit. However, whilst this can be done for many of the components within the integrated circuit, including access logic circuitry associated with the memory device, it is often the case that a higher voltage is needed to drive the array of memory cells within the memory device in order to enhance the stability of those cells. Hence, embedded SRAM bit cells may use a higher voltage supply to guarantee state retention, whilst the rest of the system, including the access logic circuitry employed to access those bit cells within the memory device, may use a lower voltage supply to reduce power consumption. In order to maintain performance, and reduce switching power, level shifters are provided to pass signals between these domains.
It is often the case that combinatorial circuits will exist in regions of the integrated circuit where signals are to be passed between different voltage domains. Combinatorial circuits can take a variety of forms, for example adders, subtractors, multiplexers, demultiplexers, encoders, decoders, etc. Such circuits produce an output signal which is a pure function of the presented input signals. Considering the earlier example of a voltage domain transition between the access logic circuitry of the memory device operating in a lower voltage domain, and the actual bit cells of the memory device operating in a higher voltage domain, an example of such a combinatorial circuit is a word line driver circuit used to generate a word line signal associated with a row of bit cells within the memory array. Such a word line driver circuit operates as a decoder to determine, based on a plurality of input signals, whether to assert the word line signal. An example of a known word line driver circuit is illustrated in FIG. 1.
As can be seen from FIG. 1, the word line driver circuit basically consists of a NAND gate formed by a plurality of PMOS transistors 4, 5, 6 in parallel, and a stack of NMOS transistors 1, 2, 3, with the output of the NAND gate then passed through an inverter formed by a PMOS transistor 8 in series with an NMOS transistor 7. In the example of FIG. 1, it is assumed that both the NAND gate and the inverter operate in the higher voltage domain, receiving a supply voltage VDDC associated with that higher voltage domain. However, it is assumed that the input signals A and B, and typically also the clock signal CK, are generated by components in the low voltage domain.
As will be understood by those skilled in the art, pre-decode circuitry forming part of the access logic circuitry of the memory device will typically receive an address, and perform a number of pre-decode operations in order to generate two data bits provided to each word line driver circuit, these data bits being indicated in FIG. 1 as the signals A and B. If both of these bits are asserted at a logic one value, then during a particular phase of the clock signal the word line driver circuit is arranged to assert the word line signal. In the example of FIG. 1, the predetermined phase of the clock signal is the logic one phase. Accordingly, if both of the signals A and B are asserted at a logic one level in the lower voltage domain, they will turn on the NMOS transistors 2, 3, and when the clock signal is also high, turning on the NMOS transistor 1, this will cause the output of the NAND gate to transition to a logic zero level, since all of the PMOS transistors 4, 5, 6 will at this stage be turned off. The operation of the inverter will then cause a logic one value to be asserted on the word line, this logic one value being at the high voltage VDDC.
Hence, it can be seen that the circuitry of FIG. 1 can perform level shifting whilst also decoding the input signals in order to generate the required word line signal. However, it should be noted that because the signals A and B (and optionally also the clock signal CK) are generated in the low voltage domain, then during the scenario discussed above, the NMOS transistors will not be fully turned on, and also the PMOS transistors within the NAND gate will not be fully turned off. Accordingly, as the voltage difference between the lower voltage domain and the higher voltage domain increases, this will increase the latency of operation of the NAND gate, and hence impact performance. As the voltage difference increases still further, this can result in the failure of the word line driver circuitry, and accordingly the circuitry of FIG. 1 can only be used in situations where there is a relatively small voltage difference between the lower voltage domain and the higher voltage domain.
Also shown in FIG. 1 is a PMOS control header transistor 9, which can be used to reduce leakage through the inverter during periods of time where the word line driver circuitry is not being used. In particular, in this example, it is assumed that the chip enable (CEN) signal is asserted at a logic zero level when the portion of the SRAM memory connected to the wordline is active, hence turning on the transistor 9 and connecting the inverter to the VDDC supply. Conversely, when the chip enable signal is de-asserted at a logic one value, this turns off the PMOS transistor 9, hence avoiding leakage current being drawn through the inverter.
Whilst the word line driver circuitry of FIG. 1 offers a suitable solution when the voltage difference between the lower voltage domain and the higher voltage domain is relatively small, the voltage differences are becoming larger and larger in modern data processing systems. For example, the difference in voltage between the lower voltage domain and the higher voltage domain can be as larger as 400 mV when taking into account power supply tolerance variation and IR drop. With such large differences between the two voltage domains, the word line driver circuitry of FIG. 1 cannot be used.
Commonly owned co-pending patent application US 2008/0157848 A1, the entire contents of which are hereby incorporated by reference, describes a level shifting circuit for use between voltage domains which is able to operate efficiently even when there is a relatively large voltage difference between the lower voltage domain and the higher voltage domain. Hence, an input signal provided to that level shifting circuit can be upshifted to a significantly higher voltage domain. Accordingly, one possible approach would be to operate the word line driver circuitry entirely in the lower voltage domain, and then use such a level shifting circuit as described in the above patent application to boost the output signal to the higher voltage domain. However, such an approach would be have a significant performance impact, and would also have a relatively large power consumption, due to the presence of the two separate circuits.
Accordingly, it would be desirable to provide an improved circuit for performing combinatorial operations, such as the above described decoding operation, whilst also allowing a larger voltage level shifting range to be accommodated.